1. Field of the Invention
The present invention relates to a method for controlling the operation of a sense amplifier for a memory device, and more particularly to a method capable of controlling an operation period of a sense amplifier according to variation of an operational frequency of a memory device.
2. Description of the Prior Art
FIG. 1 is a view for explaining a read operation and a write operation of a general memory device.
As shown in FIG. 1, during the write operation, data applied through an input/output data pad are transferred to a bit line sense amplifier through a data input buffer, a data input register, and a write driver. Also, during the read operation, cell data amplified by the bit line sense amplifier are transferred to the input/output data pad through a data sense amplifier, a pipe register, and a data output buffer.
In FIG. 1, signal “Yi” is a pulse signal for controlling the operation of data buses which connect the bit line sense amplifier with the data sense amplifier. While the signal “Yi” controlling the data buses is enabled, write data are transferred from the write driver to the bit line sense amplifier, and read data are transferred from the bit line sense amplifier to the data sense amplifier. Therefore, in order to transfer valid data during an active operation, that is, during the read operation or the write operation, the wider pulse width of the signal “Yi” is, the more profitable it becomes. This permits data to be better restored under the same “tDPL” condition, thereby also obtaining an effect of improving the “tDPL, in which the “tDPL” is a time interval from a time when a CAS pulse is generated internally by a write command to a time when a precharge pulse signal is generated internally by a precharge command. Therefore, in most cases, the pulse width of the signal “Yi” is set as large as possible and the pulse width of the signal “Yi” is reduced in use if necessary. For reference, when the operational frequency of a memory device increases, that is, when the clock period decreases, the tolerable pulse width of the signal “Yi” decreases.
Herein, the above-mentioned signal “Yi” is created by receiving a read/write strobe pulse signal “rdwtstbzp13” outputted from a read/write strobe pulse generating circuit, so the description of a read/write strobe pulse generating circuit will be followed.
FIG. 2A is a circuit diagram illustrating an example of a conventional read/write strobe pulse generating circuit, and FIG. 2B is a waveform view for explaining the operation of the circuit shown in FIG. 2A.
In FIG. 2A, signal “extyp8” and signal “icasp6” are used for making a “short” status or an “open” status between a data transmission line of a memory cell array and a data transmission line of a peripheral circuit so as to read data stored in the cell array (core region) of a memory device into the peripheral circuit and to write data applied from the peripheral circuit into the memory cell array. For convenience of description, it will be defined that one region, which includes a memory cell and a bit line sense amplifier, is called a core region, and the other region is called a peripheral circuit.
To be more specific, the signal “extyp8” is a pulse signal generated in synchronization with a clock signal when a read or a write command (burst command) is applied from outside. The signal “icasp6” is used to operate the memory device through creating a self burst operation command corresponding to a burst length, which is preset by MRS, from a point of a predetermined clock created later than a clock, to which the read or write command is applied from an exterior, by 1 period.
Signal “rdwtstbzp13” is enabled by an entire burst length which is determined by the MRS in synchronization with a burst operation command whenever the burst operation command (External=extyp8&Internal=icasp61) is enabled. That is, the signal “rdwtstbzp13” represents an activation time of an input/output sense amplifier, which is used to sufficiently amplify data transmitted from the core region into the peripheral circuit so as to transmit output data to a buffer. Also, the signal “rdwtstbzp13” is to reset a data transmission line of the peripheral circuit after amplification and transmission of data is completed.
Signal “pwrup” is used to set an initial value and is maintained at a low level after falling down to the low level from a high level. Signal “term_z” is to be used during a test mode and is maintained at a low level during a normal operation. Signal “tm_clkpulsez” is to be used during the test mode. These signals will be described in more detail when the present invention is described.
The circuit operation of FIG. 2A will be described with reference to the waveform view shown in FIG. 2B.
As shown in FIG. 2B, when a read/write command is created in synchronization with a clock signal, the pulse signal “extyp8” is generated. When the pulse signal “extyp8” is generated, a plurality of pulses “icasp6” are sequentially generated in synchronization with the following clocks. As shown in this drawing, a read/write strobe pulse signal is generated in synchronization with rising edges of the pulse signals “extyp8” and “icasp6”.
Referring to the conventional circuit of FIG. 2, it is understood that a pulse width control section 200 determining a pulse width of the read/write strobe pulse signal “rdwtstbzp13” has been set regardless of an operational frequency of the memory device. That is, a delay time of a delay unit 20 in the pulse width control section 200 is fixed, so that there is no alternative but to output a signal having a constant pulse width from the pulse width control section 200.
However, in the case in which the operational frequency of the memory device is varied, it is necessary to control the pulse width of the read/write strobe pulse signal “rdwtstbzp13”.
Conventionally, when the operational frequency of the memory device is varied, it is necessary to adjust the delay time of the delay unit 20 by correcting a metal option during FIB work. However, such a conventional method may cause an expensive cost and much time.